1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly to integrated circuit packaging and interconnections.
2. Description of the Related Art
As seen in FIG. 1, a typical digital electronic circuit includes a number of digital integrated circuits, such as IC1 and IC2, and discrete active or passive components such as capacitor C. The various components of the digital circuit are coupled together by means of a printed circuit board P having a number of conductive traces (such as traces T1 and T2) formed along one or more surfaces of the board.
When operating digital circuits at high speeds there is the problem of supplying charge quickly enough to the rapidly switching devices of the integrated circuits. This problem can be partially ameliorated by placing a capacitor between power and ground near each integrated circuit package to serve as a local charge storage device. However, at very high switching speeds even a large capacitor placed very close to an integrated circuit package cannot supply charge sufficiently rapidly to the devices within the integrated circuit. This is due to tiny inductances in the leads of the capacitor and the integrated circuit, the connecting traces, etc. which create substantial electrical impedance at high operating frequencies.
FIG. 2 is a schematic representation of the circuit of FIG. 1. IC1 includes a transmitter, i.e. a device which sends signals off-chip, while IC2 includes a receiver of those signals. The IC1 transmitter includes a driver D1 and the IC2 receiver includes a driver/receiver D2. Inductors L1 and L2 represent the lead inductances of capacitor C and inductance L3 represents the inductance of the power plane between the power lead of capacitor C and the power lead of IC1. Inductances L5, L6 and L9 are the inductances of leads to the integrated circuit IC1 for power, ground, and signal output, respectively. The transmission line (X-LINE) of the model corresponds to the trace T2 coupling IC1 to IC2, while the inductances L8 and L10 are lead capacitances for integrated circuit IC2. Resistor R.sub.t is a termination resistance which matches the impedance of the X-LINE. Finally, inductances L7 and L4 are the inductances of the ground path from IC2 to the capacitor ground lead.
When driver D1 is activated, a typical current path is as follows: L1.fwdarw.L3.fwdarw.L5.fwdarw.L9.fwdarw.X-LINE.fwdarw.L8.fwdarw.R.sub.t .fwdarw.L10.fwdarw.L7.fwdarw.L4.fwdarw.L2.fwdarw.C. The total inductance of the loop is then L1+L3+L5+L9+L8+L10+L7+L4+L2, which is often several nanohenrys. Since the expression for current in an inductive circuit is given by i=V/R.times.e.sup.-tR/L, an increase in inductance will increase the time constant L/R of the circuit, thereby reducing the speed at which the circuit can be operated.
Another problem with high speed operation is that the voltage at V.sub.HI (node 1) will drop by the amount L.times.dI/dt where dI is the change in current and dt is the turn-on time of the driver. For digital bipolar circuits, dI is approximately 20 milliamperes and dt is approximately 0.5 nanoseconds. The drop dV.sub.max allowable at node 1 is typically 200 millivolts or less. The dV.sub.max puts an upper limit on L, i.e. L&lt;=dV.sub.max .times.1/(dI/dt) or, in the present example, L must be less than or equal to approximately 5 nanohenrys. If only one driver on IC1 were to switch at a time, this upper limit for L can be easily satisfied. However, it is not unusual for an IC to have 200 drivers, requiring the total inductance to be less than or equal to 5 nh/200 or 25 picohenrys in the worst-case scenario where all of the drivers switch simultaneously. This is difficult or impossible to achieve with conventional packaging and interconnecting technologies.
Another problem with prior art structures is that of providing the proper ground and power potentials to the various components within an integrated circuit. Since most TTL integrated circuits operate at 5 volts, a voltage drop of as little as one volt along a power plane can cause components of the integrated circuit to behave erratically and unpredictably. This problem has been addressed in the prior art by increasing the area and/or thickness of the power plane. The unfortunate trade-offs of this prior art solution are increased manufacturing costs and lowered circuit density.